1. Field of the Invention
Embodiments of the present invention relate generally to integrated circuit chip packaging and, more specifically, a method for creating decoupling capacitors (decaps) with buried through-silicon vias (B-TSVs) in a packaging substrate and a cost effective process for manufacturing B-TSVs decaps by leveraging an etch loading effect.
2. Background
In the packaging of integrated circuit (IC) chips, one or more IC chips are usually mounted on a top surface of a packaging substrate. Through silicon vias (TSVs) provide vertical pathways to facilitate electrical connections of the IC chip to a motherboard or other printed circuit board (PCB). To accommodate multiple device dies, an interposer is typically used to bond device dies thereon, with through silicon vias (TSVs) formed in the interposer. Generally, TSV interposer has emerged as a good solution to provide high wiring density interconnection, minimizing coefficient of thermal expansion mismatch between the copper/low-k die and the copper filled TSV interposer and improving electrical performance due to shorter interconnection distances from the chip to the substrate.
Through silicon vias (TSVs) in the interposer are usually formed by etching silicon material through the interposer. Strict control of the etch rate and profile is required for TSVs to be properly formed. The etch rate of silicon depends in part on the total exposed area of the vias being formed in a unit substrate area. The variation in the etch rate dependent on differences in local amount exposed area of the vias per unit substrate area is called microloading. For example, regions having a large amount of exposed via area per unit substrate area will generally etch slower than regions having a small amount of exposed via area per unit substrate area due to microloading. The microloading effect may cause TSVs formed in a dense pattern to have a 10 percent etch rate reduction as compared to TSVs formed in an isolated (i.e., less dense) pattern. The variation in etch rate may cause blind-vias (i.e., vias that do not extend completely through the silicon) to be formed. Conventionally, blind-vias formed while etching TSVs are of little value, and can contribute to defects in the overall package structure.
To eliminate blind-vias, fabricators perform additional and complicated process steps after the typical TSV etching process in order to open up the blind-vias so that they may be utilized to form a complete set of through vias. The additional process step of opening the blind-vias to convert them to through vias is expensive, and may also risk the introduction of process defects which may undesirably decrease production yields.